The present invention is related to communication systems which use a hybrid automatic repeat request (H-ARQ) scheme for improving quality of service, (e.g. system throughput). More particularly, the present invention is directed to a system and method for reducing the latency of the H-ARQ reordering buffers within a receiver.
H-ARQ processing is a scheme comprising multiple parallel ARQ processors whereby each processor repeatedly transmits several sequential attempts of a data block until the transmission is successful to ensure that each block of data is received without an error. Referring to FIG. 1, a simplified flow diagram of the data flow between a Node B (shown at the bottom of FIG. 1) and a UE (shown at the top of FIG. 1) is shown. Protocol data units from higher level processing are scheduled and may be multiplexed into one data block. A data block can only contain protocol data units of higher layers of the same priority. A unique Transmission Sequence Number (TSN) is assigned to each data block by the scheduler. The higher layers may provide a plurality of streams of different priorities of protocol data units, each priority having a sequence of TSNs. The scheduler then dispatches the blocks to the plurality of H-ARQ processors P1B-P5B. Each H-ARQ processor P1B-P5B is responsible for processing a single block of data at a time. For example, as shown in FIG. 1, the Priority 1 protocol data units comprise a sequence illustrated as B11-B1N. Likewise, the Priority 2 protocol data units are sequenced from B21-B2N and the Priority 3 protocol data units are sequenced from B31-B3N. These protocol data units are scheduled (and may be multiplexed) and affixed a TSN by the common scheduler. For purposes of describing the invention, we assume one protocol data unit for one data block. After a data block is scheduled to be processed by a particular processor P1B-P5B, each data block is associated with a processor identifier, which identifies the processor P1B-P5B that processes the data block. It should be understood by those of skill in the art that this association may include xe2x80x9ctaggingxe2x80x9d the data block or may comprise control channel signaling, whereby a control channel provides signaling from the Node B to the UE that a particular data block is associated with a particular transmit processor P1B-P5B. The data blocks are then input into the scheduled Node B H-ARQ processors P1B-P5B which receive and process each data block. Each Node B H-ARQ processor P1B-P5B corresponds to an H-ARQ processor P1UE-P5UE within the UE. Accordingly, the first H-ARQ processor P1B in the Node B communicates with the first H-ARQ processor P1UE in the UE. Likewise, the second H-ARQ processor P2B in the Node B communicates with the second H-ARQ processor P2UE in the UE, and so on for the remaining H-ARQ processors P3B-P5B in the Node B and their counterpart H-ARQ processors P3UE-P5UE respectively within the UE. The H-ARQ processes are timely multiplexed onto the air interface and there is only one transmission of an H-ARQ on the air interface at one time.
For example, taking the first pair of communicating H-ARQ processors P1B and P1UE, the H-ARQ processor P1B processes a data block, for example B11, and forwards it for multiplexing and transmitting it over the air interface. When this data block B11 is received by the first H-ARQ processor P1UE, the processor P1UE determines whether or not it was received without error. If the data block B11 was received without error, the first H-ARQ processor P1UE transmits an acknowledgment (ACK) to indicate to the transmitting H-ARQ processor P1B that it has been successfully received. On the contrary, if there is an error in the received data block B11, the receiving H-ARQ processor P1UE transmits a negative acknowledgment (NACK) to the transmitting H-ARQ processor P1B. This process continues until the transmitting processor P1B receives an ACK for the data block B11. Once an ACK is received, that processor P1B is xe2x80x9creleasedxe2x80x9d for processing another data block. The scheduler will assign the processor P1B another data block if available.
As graphically illustrated in FIG. 1, the scheduler knows of the release of the processor P1B by receiving the ACK/NACK, or may use some other signaling scheme that is well known in the art.
Once the receiving H-ARQ processors P1UE-P5UE process each data block, they are forwarded to the reordering buffers R1, R2, R3 based on their priority; one reordering buffer for each priority level of data. For example, Priority 1 data block B11-B1N will be received and reordered in the Priority 1 reordering buffer R1; Priority 2 data blocks B21-B2N will be received and reordered in the Priority 2 reordering buffer R2; and the Priority 3 data blocks B31-B3N will be received and reordered by the Priority 3 reordering buffer R3. Due to the pre-processing of the data blocks by the receiving H-ARQ processors P1UE-P5UE and the ACK/NACK acknowledgement procedure, the data blocks are often received in an order that is not sequential with respect to their TSNs. The reordering buffers R1-R3 receive the out-of-sequence data blocks and attempt to reorder the data blocks in a sequential manner prior to forwarding onto the RLC layer. For example, the Priority 1 reordering buffer R1 receives and reorders the first four Priority 1 data blocks B11-B14. As the data blocks are received and reordered, they will be passed to the RLC layer.
On the receiving side, the UE MAC-hs, (which has been graphically illustrated as MAC-hs control), reads the H-ARQ processor ID, whether it is sent on a control channel such as the HS-SCCH or whether the data block has been tagged, to determine which H-ARQ processor P1UE-P5UE has been used. If the UE receives another data block to be processed by the same H-ARQ processor P1UE-P5UE, the UE knows that that particular H-ARQ processor P1UE-P5UE has been released regardless of whether or not the previous data block processed by that H-ARQ processor P1UE-P5UE has been successfully received or not.
This process has several drawbacks that can cause a reordering buffer to xe2x80x9cstall;xe2x80x9d whereby the reordering buffer continues to wait for a data block which may never be transmitted. For example, referring to the Priority 2 reordering buffer R2, the third data block B23 is missing. Using the current process, the reordering buffer R2 will initiate a timer when the subsequent data block B24 is received. The reordering buffer R2 will wait a predetermined duration as set by the timer to receive the missing data block B23 until the timer xe2x80x9ctimes out.xe2x80x9d If it does not receive that data block after the xe2x80x9ctime out,xe2x80x9d it forwards the data blocks B21-B24, as well as subsequent data blocks up to the first missing data block, to the RLC layer. The RLC layer can then perform higher level processing to recover the missed data block.
There are several scenarios which increase the probability of reorder buffer stalling. For example, there are scenarios that data blocks of higher priority preempt data blocks of lower priority in H-ARQ transmissions; in this case, a H-ARQ process is released to serve a data block of higher priority regardless of whether the transmission of the data block of lower priority is not successful. The reordering buffer cannot tell whether a missing data block has been preempted by a higher priority data block or whether the data block is still in H-ARQ transmission. For example, the Priority 2 reordering buffer R2 does not know whether its third data block B23 was preempted by one of the Priority 1 data blocks B11-B14 or whether its data block B23 is still in transmission. Where its third data block B23 was preempted and no data block was received with the same H-ARQ processor as that of the data block B23 within the predetermined duration, the Priority 2 reordering buffer R2 must wait the entire timeout period before forwarding the information to upper layers for further processing.
A second scenario which increases the probability of stalling occurs during low to medium load conditions. When the UE is receiving a lower volume of data blocks, the new incoming data blocks are slow to flush the reordering buffer. For example, referring to the Priority 3 reordering buffer R3, the reordering buffer R3 does not know the status of the next data block B34, It may have been preempted by a higher priority data block, the transmission of the data block B34 may have failed or data block B33 may be the last data block in the sequence of data blocks B31-B3N. If the data block B35 is received before data block B34, a timer is initiated. However, if low to medium load conditions are present or the data is at the end of a file transfer, there are no more data blocks that may use the same H-ARQ processor as B34. The UE will have difficulty determining whether B34 is abandoned. In this case, the Priority 3 reordering buffer R3 must wait the entire xe2x80x9ctimeout periodxe2x80x9d before forwarding the information to upper layers for further processing.
Finally, since the air interface is not completely reliable, a NACK, which is somehow transformed or interpolated as an ACK by the transmitting H-ARQ processors P1B-P5B will mean that the transmission of the particular data block has failed and will not subsequently be re-transmitted. The reordering buffers R1-R3 do not know of this miscommunication and the lost data block. The reordering buffers will again become stalled waiting for a timer to indicate the occurrence of a missing data block.
Although these scenarios are somewhat alleviated by the MAC-hs layer which instructs the particular reordering buffer R1-R3 to forward data to higher layers when a receiving H-ARQ processor P1UE-P5UE has been released, this is only a minimal improvement.
The present invention uses a Last-In-First-Out (LIFO) policy for loading the transmitting H-ARQ processors. A scheduler assigns the next sequential data block to the most recently released H-ARQ processor. The LIFO loading policy increases the probability that the UE will be able to determine at an earlier time whether the missed TSN is due to delay in retransmission or due to the release of a transmission by the Node B by reading the new H-ARQ processor identifier (ID). Once the UE MAC-hs receives a new TSN with the same H-ARQ processor ID, the missed data block with the old TSN is forwarded to the higher layer processes to take the appropriate action for data block recovery.